…just this guy, you know.

  • 2 Posts
  • 176 Comments
Joined 2 years ago
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Cake day: May 7th, 2023

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  • ok. my apologizes.

    there really are tons of things to consider with that question. RISC has historically allowed for faster clocking and fewer cycles per instruction, so thats a win. RISC also requires more instructions per useful operation and also blows up the binary size, so… :-(

    all things being equal (hahaha) RISC has more headroom and legroom for future improvements that dont complecate the silicon to extreme degrees. the vast majority of CISC designs are now pretty RISC-like at their cores, but the software interface remains CISC and, I think, complicates and limits variety and advancement.

    imho, a properly spec’d RISC processor and a carefully designed compiler, cycle for cycle, macro for macro and watt for watt outperforms a CISC design (even with a RISC-like core). major computing holy wars are been waged over this for decades.

    all I currently have access to are older studies that show mixed general purpose results on RISC vs CISC (performance, not power efficiency), but if I had to make a choice about what my future ideal processor would be, it would be RISC core and RISC instruction set architecture simply due to less complexity, more efficient use of wafer space and lower power requirements. then we start talking about massively parallel RISC in tiny spaces and, for many (but not all) workloads, thats a big win.





  • great reply. I am not saying RISC is the panecea, what I am saying is that there are more options for workload optimization further up the stack and rebalancing of the intelligence from the silicon to the software is an advantage.

    some time ago most CISC core design become more RISC-y and, to indulge in some ISA snobbery, I just want to slash and burn the CISC presentation to the software layer. memory is cheap, bus bandwidth is insane - simplification on the ISA just seems like a hardware complexity win all around and I am willing to pay for that in compiler complexity that incorporates changes more easily than hardware or CISC microcode.

    RISC-V’s challenge is can they standardise the software ecosystem enough[…]

    agreed. this is why I say my wait may be coming to an end.

    personally, I think RISC is the more flexible design in almost every usecase. cycle for cycle, RISC hits the right buttons for me across the widest number of situations once we get above the “magic hardware” layer. willing to flog the CISC vs RiSC horse convo if you have recent information, and thanks for the response.








  • depending on specs it will be a little power hungry, but a good virtualization platform.

    yes, the power supplies are likely redundant and the server will complain if they are not both powered.

    it will use a VGA connection, but you should be ale to find cheap VGA monitors or cheap adapters.

    RAID controllerfor those drives? how many processors and cores? how much RAM? what OS are you planning on running on it? iDRAC included? (if so, likely idrac6, but still usable)

    this hardware is very well supported by linux - I have used these older servers extensively. your boss was right to be excited for you. its a great exploration platform that you will be able to do lots of things with.

    fire up a live linux distro and get detailed specs on the box - that will guide what you can play with right away.